Freescale Semiconductor /MKL28T7_CORE1 /SCG /SPLLDIV

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as SPLLDIV

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (000)SPLLDIV1 0 (000)SPLLDIV2 0 (000)SPLLDIV3

SPLLDIV3=000, SPLLDIV2=000, SPLLDIV1=000

Description

System PLL Divide Register

Fields

SPLLDIV1

System PLL Clock Divide 1

0 (000): Clock disabled

1 (001): Divide by 1

2 (010): Divide by 2

3 (011): Divide by 4

4 (100): Divide by 8

5 (101): Divide by 16

6 (110): Divide by 32

7 (111): Divide by 64

SPLLDIV2

System PLL Clock Divide 2

0 (000): Clock disabled

1 (001): Divide by 1

2 (010): Divide by 2

3 (011): Divide by 4

4 (100): Divide by 8

5 (101): Divide by 16

6 (110): Divide by 32

7 (111): Divide by 64

SPLLDIV3

System PLL Clock Divide 3

0 (000): Clock disabled

1 (001): Divide by 1

2 (010): Divide by 2

3 (011): Divide by 4

4 (100): Divide by 8

5 (101): Divide by 16

6 (110): Divide by 32

7 (111): Divide by 64

Links

() ()